Publications

Journal Articles

• W. R. Davis, J. Wilson, S. Mick, J. Xu, H. Hua, C. Mineo, A. M. Sule, M. Steer, and P. D. Franzon, “Demystifying 3D ICs: The Pros and Cons of Going Vertical,” IEEE Design & Test of Computers, vol. 22, no. 6, pp. 498-510, Nov.-Dec. 2005.
• E. Yeo, S. Augsburger, W. R. Davis, and B. Nikolić, “500 Mb/s Soft Output Viterbi Decoder,” IEEE Journal of Solid State Circuits, vol. 38, no. 7, pp. 1234-41, July 2003.
• W. R. Davis, N. Zhang, K. Camera, D. Marković, T. Smilkstein, M. J. Ammer, E. Yeo, S. Augsburger, B. Nikolić, and R. W. Brodersen, “A Design Environment for High-Throughput, Low-Power Dedicated Signal Processing Systems,” IEEE Journal of Solid State Circuits, vol. 37, no. 3, pp. 420-31, March 2002.
  

Conference Papers

• R. Hourani, R. Jenkal, R. Davis, and W. Alexander, “Tool Integration for Signal Processing Architectural Exploration,” Electronic Design Process (EDP) Workshop, Apr. 2006.
• H. Hua, C. Mineo, K. Schoenfliess, A. Sule, S. Melamed, W. R. Davis, “Performance Trend in Three-Dimensional Integrated Circuits,” to appear at the IEEE International Interconnect Technology Conference, June 2006.
• H. Hua, C. Mineo, K. Schoenfliess, A. Sule, S. Melamed, R. Jenkal, and W. R. Davis, “Exploring Compromises among Timing, Power and Temperature in Three-Dimensional Integrated Circuits,” to appear at the Design Automation Conference, July 2006.
• S. Luniya, W. Batty, V. Caccamesi, M. Garcia, C. Christoffersen, S. Melamed, W. R. Davis, and M. Steer, “Compact Electrothermal Modeling of an X-band MMIC,” Proceedings of the International Microwave Symposium (IMS), June 2006.
• H. Hua, A. Sule, C. Mineo, and W. R. Davis, “Pre-route Net Classing for Crosstalk Avoidance” Cadence Designer Network Live Conference (CDNLive), San Jose, CA, Sept. 12-13, 2005.
• W. R. Davis, A. M. Sule, and H. Hua, “Multi-Parameter Power Minimization of Synthesized Datapaths,” IEEE Computer Society Annual Sympsium on VLSI (IS-VLSI), pp. 151-157,  Feb. 2004
• W. R. Davis, “Getting High-Performance Silicon from System-Level Design,” IEEE Computer Society Annual Sympsium on VLSI (IS-VLSI), pp. 238-243, Feb. 2003.
• E. Yeo, S. Augsburger, W. R. Davis, and B. Nikolić, “Implementation of high throughput soft output viterbi decoders,” IEEE Workshop on Signal Processing Systems (SIPS), pp. 146-151, Oct. 2002.
• E. Yeo, S. Augsburger, W. R. Davis, and B. Nikolić, “500 Mb/s Soft Output Viterbi Decoder,” European Solid-State Circuits Conference (ESSCIRC), pp. 523-526, Sep. 2002.
• W. R. Davis, N. Zhang, K. Camera, F. Chen, D. Marković, N. Chan, B. Nikolic, R. W. Brodersen, “A Design Environment for High Throughput, Low Power Dedicated Signal Processing Systems”, IEEE Custom Integrated Circuits Conference (CICC), pp. 545-548, May 2001.

Invited Papers

• W. R. Davis, H. Hua, A. Sule, C. Mineo, S. Melamed, M. Steer, and P. D. Franzon, “Wire-Delay Reduction Analysis of a 3-Tier, 8-Point Fast Fourier Transform 3D-IC,” VLSI Multilevel Interconnection (VMIC) Conference, Oct. 2005.
• W. R. Davis, N. Zhang, K. Camera, D. Marković, T. Smilkstein, N. Chan, M. J. Ammer, E. Yeo, B. Nikolić, R. W. Brodersen, "An Automated Design Flow for Low-Power, High-Throughput Dedicated Signal Processing Systems," Proc. of the Asilomar Conf. on Signals, Systems and Computers, pp. 475-480, Nov. 2001.
  

Invited Research Presentations

• “Demystifying 3D ICs: The Pros and Cons of Going Vertical,” Virginia Tech ECE Department Seminar, Blacksburg, VA, Apr. 14, 2006.
• “OpenAccess Tools for 3D Integration,” OpenAccess Conference, San Jose, CA, Nov. 10, 2005.
• “Automated Design Flows for High-Performance Systems,” OpenAccess Conference, San Jose, CA, Feb. 11, 2003.
• “An Automated Design Flow for Low-Power, High-Throughput Dedicated Signal Processing Systems,” MathWorks, Inc. seminar Innovation First: System Level Design for DSP and Communications, Waltham, MA, Dec. 4, 2001.
•  “Design Technology for Low Power Radio Systems,” Computer Aided Network Design Workshop (CANDE), Grand Teton, WY, Sept. 20-22, 2001.
  

Panel Discussions

•  “How Much Asynchrony Do We Want?” IEEE Computer Society Annual Symposium on VLSI (IS-VLSI),  Feb. 2004

Book Chapters

• K. Kuusilinna, C. Chang, H. M. Bluethgen, W. R. Davis, B. Richards, B. Nikolić, and R. W. Brodersen, “Real-Time System-on-a-Chip Emulation,” Winning the SOC Revolution: Experiences in Real Design, Kluwer Academic Press, Edited by Grant Martin and Henry Chang, May 2003.

Dissertation

• W. R. Davis, A Hierarchical, Automated Design Environment for Low-Power, High-Throughput Digital Signal Processing ICs, PhD Dissertation, University of California, Berkeley, January 2002.