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Research Projects
The 3D IC Project aims to develop design kits, circuits, and methodologies to allow chip designs that take full advantage of emerging three-dimensional processing technology. Although 3D ICs offer shorter global wires, the added heat erodes the performance gains. Much of the work involves comparison of designs in 3D ICs to traditional planar technology, to see if 3D processing really provides any capability that cannot be achieved any other way.
Publications:
- W. R. Davis, J. Wilson, S. Mick, J. Xu, H. Hua, C. Mineo, A. M. Sule, M. Steer, and P. D. Franzon, “Demystifying 3D ICs: The Pros and Cons of Going Vertical,” IEEE Design & Test of Computers, vol. 22, no. 6, pp. 498-510, Nov.-Dec. 2005.
- H. Hua, C. Mineo, K. Schoenfliess, A. Sule, S. Melamed, W. R. Davis, “Performance Trend in Three-Dimensional Integrated Circuits,” to appear at the IEEE International Interconnect Technology Conference, June 2006.
- H. Hua, C. Mineo, K. Schoenfliess, A. Sule, S. Melamed, R. Jenkal, and W. R. Davis, “Exploring Compromises among Timing, Power and Temperature in Three-Dimensional Integrated Circuits,” to appear at the Design Automation Conference, July 2006.
- S. Luniya, W. Batty, V. Caccamesi, M. Garcia, C. Christoffersen, S. Melamed, W. R. Davis, and M. Steer, “Compact Electrothermal Modeling of an X-band MMIC,” Proceedings of the International Microwave Symposium (IMS), June 2006.
- W. R. Davis, H. Hua, A. Sule, C. Mineo, S. Melamed, M. Steer, and P. D. Franzon, “Wire-Delay Reduction Analysis of a 3-Tier, 8-Point Fast Fourier Transform 3D-IC,” VLSI Multilevel Interconnection (VMIC) Conference, Oct. 2005.
The SSHAFT project is an extension of the old "Simulink to Silicon Hierarchical Automated Flow Tool" to create an environment for documenting and delivering an IC-design tool flow.
Publications:
- W. R. Davis, “Getting High-Performance Silicon from System-Level Design,” IEEE Computer Society Annual Sympsium on VLSI (IS-VLSI), pp. 238-243, Feb. 2003.
- E. Yeo, S. Augsburger, W. R. Davis, and B. Nikolić, “500 Mb/s Soft Output Viterbi Decoder,” IEEE Journal of Solid State Circuits, vol. 38, no. 7, pp. 1234-41, July 2003.
- W. R. Davis, N. Zhang, K. Camera, D. Marković, T. Smilkstein, M. J. Ammer, E. Yeo, S. Augsburger, B. Nikolić, and R. W. Brodersen, “A Design Environment for High-Throughput, Low-Power Dedicated Signal Processing Systems,” IEEE Journal of Solid State Circuits, vol. 37, no. 3, pp. 420-31, March 2002.
Adjacency Constrained Wire-Planning
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Multi-Parameter Power Minimization
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