| Derived Metrics |
| Graduated instructions per cycle |
1.518 |
| Floating point operations per cycle |
0.23 |
| Data references per instruction |
0.052 |
| Ratio of graduated instructions to issued instructions |
0.938 |
| L1 instruction cache miss ratio |
0.006 |
| L1 data cache read miss ratio |
0.049 |
| L3 data cache miss ratio |
0.233 |
| L3 cache data read ratio |
0.616 |
| L3 cache instruction miss ratio |
0.194 |
| Ratio of mispredicted to correctly predicted branches |
0.059 |
| L3 cache data hit rate |
0.631 |
| L3 cache line reuse (data) |
1.707 |
| Bandwidth used to L1 cache (MB/s) |
410.55 |
| Bandwidth used to L2 cache (MB/s) |
1435.367 |
| Bandwidth used to L3 cache (MB/s) |
527.365 |
| Percentage of cycles with no instruction issue |
57.59% |
| Percentage of cycles stalled on any resource |
33.26% |
| MIPS (CPU cycles) |
2270.467 |
| MIPS (wall clock) |
2227.146 |
| Processor utilization |
98.09% |
| PAPI Event |
Counter Value |
| PAPI_BR_MSP |
7366738650 |
| PAPI_BR_PRC |
125672381082 |
| PAPI_FP_OPS |
443347620643 |
| PAPI_FP_STAL |
369576680331 |
| PAPI_L1_DCA |
151559454268 |
| PAPI_L1_DCH |
144983606882 |
| PAPI_L1_DCM |
7490663647 |
| PAPI_L1_ICR |
734335415209 |
| PAPI_L1_TCM |
8265477672 |
| PAPI_L2_DCA |
380075378226 |
| PAPI_L2_DCM |
14331711569 |
| PAPI_L2_DCR |
197045457701 |
| PAPI_L2_DCW |
182778128825 |
| PAPI_L2_ICR |
4346445637 |
| PAPI_L2_TCM |
14448905327 |
| PAPI_L3_DCA |
22711676153 |
| PAPI_L3_DCH |
9056860249 |
| PAPI_L3_DCM |
5294352688 |
| PAPI_L3_DCR |
13998394421 |
| PAPI_L3_DCW |
287852385 |
| PAPI_L3_ICM |
23267006 |
| PAPI_L3_ICR |
120006904 |
| PAPI_L3_TCM |
5308646400 |
| PAPI_LD_INS |
309088898904 |
| PAPI_RES_STL |
641141324769 |
| PAPI_SR_INS |
182381613274 |
| PAPI_STL_CCY |
1144856437558 |
| PAPI_STL_ICY |
1110047416275 |
| PAPI_TLB_TL |
1035831983 |
| PAPI_TOT_CYC |
1927552210353 |
| PAPI_TOT_IIS |
3119690833303 |
| PAPI_TOT_INS |
2925480934384 |
| General Run Information |
| Date |
Tue Oct 4 09:45:49 2005 |
| User |
sarats |
| Hostname |
tg-c623 |
| Wall Clock (ticks) |
1965045629692 |
| Wall Clock (seconds) |
1313.556 |
| System Information |
| Total memory |
4009.59MB |
| Page size |
16KB |
| Processors |
2 |
| Processor Details |
| Vendor |
Intel |
| Family |
Itanium 2 |
| Revision |
5 |
| Clock Speed (MHz) |
1495.974 |
| Cache Levels |
3 |
| Cache Details |
| Type |
Level |
Size |
Line Size |
Associativity |
| data |
1 |
16KB |
64B |
4-way (set) |
| instruction |
1 |
16KB |
64B |
4-way (set) |
| unified |
2 |
256KB |
128B |
8-way (set) |
| unified |
3 |
6144KB |
128B |
24-way (set) |
|