PerfSuite Hardware Performance Summary Report Version : 1.0 Created : Fri Oct 07 02:19:39 PM CDT 2005 Generator : psprocess 0.2 XML Source : B2.16.xml Execution Information ============================================================================================ Date : Tue Oct 04 02:05:59 AM CDT 2005 Hosts : tg-c586 tg-c587 tg-c625 tg-c626 tg-c627 tg-c628 tg-c630 tg-c879 Users : sarats Minimum and Maximum Min Max ============================================================================================ % CPU utilization..................................... 98.53 [tg-c879] 99.40 [tg-c879] % cycles stalled on any resource...................... 40.08 [tg-c587] 40.79 [tg-c630] Bandwidth used to level 1 cache (MB/s)................ 147.82 [tg-c626] 160.09 [tg-c625] Bandwidth used to level 2 cache (MB/s)................ 1781.16 [tg-c628] 1927.10 [tg-c586] Bandwidth used to level 3 cache (MB/s)................ 403.65 [tg-c587] 424.75 [tg-c879] CPU time (seconds).................................... 3690.87 [tg-c879] 3723.55 [tg-c879] Floating point operations per cycle................... 0.37 [tg-c586] 0.38 [tg-c879] Floating point operations per graduated instruction... 0.19 [tg-c879] 0.20 [tg-c630] Graduated instructions per cycle...................... 1.92 [tg-c630] 1.94 [tg-c879] Graduated instructions per issued instruction......... 0.92 [tg-c630] 0.93 [tg-c628] Issued instructions per cycle......................... 2.08 [tg-c628] 2.10 [tg-c879] Level 1 cache miss ratio (data)....................... 0.02 [tg-c879] 0.02 [tg-c626] Level 1 cache read miss ratio (instruction)........... 0.00 [tg-c587] 0.00 [tg-c879] Level 1 data cache accesses per graduated instruction. 0.03 [tg-c627] 0.04 [tg-c879] Level 1 instruction cache miss ratio.................. 0.00 [tg-c587] 0.00 [tg-c879] Level 2 cache hit rate (data)......................... -5.73 [tg-c586] -4.99 [tg-c628] Level 2 cache line reuse (data)....................... -0.85 [tg-c586] -0.83 [tg-c628] Level 2 cache miss ratio (data)....................... 0.04 [tg-c628] 0.05 [tg-c586] Level 3 cache hit rate (data)......................... 0.77 [tg-c628] 0.79 [tg-c586] Level 3 cache line reuse (data)....................... 3.32 [tg-c628] 3.66 [tg-c586] Level 3 cache miss ratio (data)....................... 0.13 [tg-c586] 0.14 [tg-c628] MFLOPS (cycles)....................................... 558.25 [tg-c586] 567.37 [tg-c879] MFLOPS (wall clock)................................... 554.66 [tg-c586] 560.68 [tg-c626] MIPS (cycles)......................................... 2865.99 [tg-c630] 2900.96 [tg-c879] MIPS (wall clock)..................................... 2827.09 [tg-c630] 2883.51 [tg-c879] Mispredicted branches per correctly predicted branch.. 0.06 [tg-c625] 0.06 [tg-c879] Percentage of cycles with no instruction completed.... 54.37 [tg-c879] 55.51 [tg-c627] Percentage of cycles with no instruction issued....... 52.63 [tg-c879] 53.61 [tg-c587] Wall clock time (seconds)............................. 3745.41 [tg-c627] 3746.41 [tg-c628] Aggregate Statistics Median Mean StdDev Sum ============================================================================================ % CPU utilization....................................... 99.02 99.01 0.33 1584.17 % cycles stalled on any resource........................ 40.42 40.43 0.20 646.82 Bandwidth used to level 1 cache (MB/s).................. 153.53 153.94 3.37 2463.06 Bandwidth used to level 2 cache (MB/s).................. 1866.49 1865.91 39.71 29854.51 Bandwidth used to level 3 cache (MB/s).................. 413.93 413.89 4.77 6622.25 CPU time (seconds)...................................... 3708.84 3708.84 12.45 59341.50 Floating point operations per cycle..................... 0.38 0.38 0.00 6.02 Floating point operations per graduated instruction..... 0.20 0.20 0.00 3.13 Graduated instructions per cycle........................ 1.93 1.93 0.01 30.81 Graduated instructions per issued instruction........... 0.92 0.92 0.00 14.79 Issued instructions per cycle........................... 2.08 2.08 0.01 33.34 Level 1 cache miss ratio (data)......................... 0.02 0.02 0.00 0.37 Level 1 cache read miss ratio (instruction)............. 0.00 0.00 0.00 0.01 Level 1 data cache accesses per graduated instruction... 0.03 0.03 0.00 0.55 Level 1 instruction cache miss ratio.................... 0.00 0.00 0.00 0.01 Level 2 cache hit rate (data)........................... -5.35 -5.32 0.20 -85.13 Level 2 cache line reuse (data)......................... -0.84 -0.84 0.01 -13.47 Level 2 cache miss ratio (data)......................... 0.04 0.04 0.00 0.70 Level 3 cache hit rate (data)........................... 0.78 0.78 0.01 12.42 Level 3 cache line reuse (data)......................... 3.50 3.48 0.10 55.60 Level 3 cache miss ratio (data)......................... 0.14 0.14 0.00 2.17 MFLOPS (cycles)......................................... 562.79 563.03 2.71 9008.52 MFLOPS (wall clock)..................................... 557.57 557.46 1.91 8919.32 MIPS (cycles)........................................... 2879.96 2880.44 9.38 46086.99 MIPS (wall clock)....................................... 2849.86 2851.96 15.41 45631.28 Mispredicted branches per correctly predicted branch.... 0.06 0.06 0.00 0.96 Percentage of cycles with no instruction completed...... 55.14 55.09 0.25 881.41 Percentage of cycles with no instruction issued......... 53.27 53.27 0.22 852.25 Wall clock time (seconds)............................... 3745.84 3745.90 0.33 59934.33