| Derived Metrics |
| Graduated instructions per cycle |
2.034 |
| Floating point operations per cycle |
0.407 |
| Data references per instruction |
0.034 |
| Ratio of graduated instructions to issued instructions |
0.916 |
| L1 instruction cache miss ratio |
0.001 |
| L1 data cache read miss ratio |
0.035 |
| L3 data cache miss ratio |
0.125 |
| L3 cache data read ratio |
0.584 |
| L3 cache instruction miss ratio |
0.044 |
| Ratio of mispredicted to correctly predicted branches |
0.052 |
| L3 cache data hit rate |
0.795 |
| L3 cache line reuse (data) |
3.871 |
| Bandwidth used to L1 cache (MB/s) |
246.564 |
| Bandwidth used to L2 cache (MB/s) |
2052.984 |
| Bandwidth used to L3 cache (MB/s) |
438.146 |
| Percentage of cycles with no instruction issue |
50.67% |
| Percentage of cycles stalled on any resource |
34.28% |
| MIPS (CPU cycles) |
3042.594 |
| MIPS (wall clock) |
3020.365 |
| Processor utilization |
99.27% |
| PAPI Event |
Counter Value |
| PAPI_BR_MSP |
10321507185 |
| PAPI_BR_PRC |
198403453250 |
| PAPI_FP_OPS |
1147924846192 |
| PAPI_FP_STAL |
793351862959 |
| PAPI_L1_DCA |
194841192332 |
| PAPI_L1_DCH |
185965521798 |
| PAPI_L1_DCM |
6868276024 |
| PAPI_L1_ICR |
1474217250685 |
| PAPI_L1_TCM |
7265631422 |
| PAPI_L2_DCA |
673044863077 |
| PAPI_L2_DCM |
30880018619 |
| PAPI_L2_DCR |
398344417509 |
| PAPI_L2_DCW |
269691933060 |
| PAPI_L2_ICR |
1421396470 |
| PAPI_L2_TCM |
30248144236 |
| PAPI_L3_DCA |
50689350128 |
| PAPI_L3_DCH |
23649816906 |
| PAPI_L3_DCM |
6339678921 |
| PAPI_L3_DCR |
29581218532 |
| PAPI_L3_DCW |
646338826 |
| PAPI_L3_ICM |
19241365 |
| PAPI_L3_ICR |
441933675 |
| PAPI_L3_TCM |
6455527316 |
| PAPI_LD_INS |
508213195056 |
| PAPI_RES_STL |
967152519365 |
| PAPI_SR_INS |
266824967046 |
| PAPI_STL_CCY |
1476859038714 |
| PAPI_STL_ICY |
1429458408470 |
| PAPI_TLB_TL |
3245954274 |
| PAPI_TOT_CYC |
2821262628891 |
| PAPI_TOT_IIS |
6265814795034 |
| PAPI_TOT_INS |
5738089116125 |
| General Run Information |
| Date |
Tue Oct 4 01:31:58 2005 |
| User |
sarats |
| Hostname |
tg-c573 |
| Wall Clock (ticks) |
2842026773741 |
| Wall Clock (seconds) |
1899.8 |
| System Information |
| Total memory |
4009.59MB |
| Page size |
16KB |
| Processors |
2 |
| Processor Details |
| Vendor |
Intel |
| Family |
Itanium 2 |
| Revision |
5 |
| Clock Speed (MHz) |
1495.961 |
| Cache Levels |
3 |
| Cache Details |
| Type |
Level |
Size |
Line Size |
Associativity |
| data |
1 |
16KB |
64B |
4-way (set) |
| instruction |
1 |
16KB |
64B |
4-way (set) |
| unified |
2 |
256KB |
128B |
8-way (set) |
| unified |
3 |
6144KB |
128B |
24-way (set) |
|