PerfSuite Hardware Performance Summary Report Version : 1.0 Created : Fri Oct 07 02:56:06 PM CDT 2005 Generator : psprocess 0.2 XML Source : BigScience.10702.xml Execution Information ============================================================================================ Date : Tue Oct 4 01:31:58 2005 Host : tg-c573 User : sarats Index Description Counter Value ============================================================================================ 1 Conditional branch instructions mispredicted..................... 10321507185 2 Conditional branch instructions correctly predicted.............. 198403453250 3 Floating point operations........................................ 1147924846192 4 Cycles the FP unit(s) are stalled................................ 793351862959 5 Level 1 data cache accesses...................................... 194841192332 6 Level 1 data cache hits.......................................... 185965521798 7 Level 1 data cache misses........................................ 6868276024 8 Level 1 instruction cache reads.................................. 1474217250685 9 Level 1 cache misses............................................. 7265631422 10 Level 2 data cache accesses...................................... 673044863077 11 Level 2 data cache misses........................................ 30880018619 12 Level 2 data cache reads......................................... 398344417509 13 Level 2 data cache writes........................................ 269691933060 14 Level 2 instruction cache reads.................................. 1421396470 15 Level 2 cache misses............................................. 30248144236 16 Level 3 data cache accesses...................................... 50689350128 17 Level 3 data cache hits.......................................... 23649816906 18 Level 3 data cache misses........................................ 6339678921 19 Level 3 data cache reads......................................... 29581218532 20 Level 3 data cache writes........................................ 646338826 21 Level 3 instruction cache misses................................. 19241365 22 Level 3 instruction cache reads.................................. 441933675 23 Level 3 cache misses............................................. 6455527316 24 Load instructions................................................ 508213195056 25 Cycles stalled on any resource................................... 967152519365 26 Store instructions............................................... 266824967046 27 Cycles with no instructions completed............................ 1476859038714 28 Cycles with no instruction issue................................. 1429458408470 29 Total translation lookaside buffer misses........................ 3245954274 30 Total cycles..................................................... 2821262628891 31 Instructions issued.............................................. 6265814795034 32 Instructions completed........................................... 5738089116125 Event Index ============================================================================================ 1: PAPI_BR_MSP 2: PAPI_BR_PRC 3: PAPI_FP_OPS 4: PAPI_FP_STAL 5: PAPI_L1_DCA 6: PAPI_L1_DCH 7: PAPI_L1_DCM 8: PAPI_L1_ICR 9: PAPI_L1_TCM 10: PAPI_L2_DCA 11: PAPI_L2_DCM 12: PAPI_L2_DCR 13: PAPI_L2_DCW 14: PAPI_L2_ICR 15: PAPI_L2_TCM 16: PAPI_L3_DCA 17: PAPI_L3_DCH 18: PAPI_L3_DCM 19: PAPI_L3_DCR 20: PAPI_L3_DCW 21: PAPI_L3_ICM 22: PAPI_L3_ICR 23: PAPI_L3_TCM 24: PAPI_LD_INS 25: PAPI_RES_STL 26: PAPI_SR_INS 27: PAPI_STL_CCY 28: PAPI_STL_ICY 29: PAPI_TLB_TL 30: PAPI_TOT_CYC 31: PAPI_TOT_IIS 32: PAPI_TOT_INS Statistics ============================================================================================ Counting domain........................................................ user Multiplexed............................................................ yes Floating point operations per cycle.................................... 0.407 Floating point operations per graduated instruction.................... 0.200 Graduated instructions per cycle....................................... 2.034 Issued instructions per cycle.......................................... 2.221 Graduated instructions per issued instruction.......................... 0.916 Level 1 instruction cache miss ratio................................... 0.001 Level 1 data cache accesses per graduated instruction.................. 0.034 Percentage of cycles with no instruction issued........................ 50.667 Percentage of cycles with no instruction completed..................... 52.347 % cycles stalled on any resource....................................... 34.281 Mispredicted branches per correctly predicted branch................... 0.052 Level 2 cache line reuse (data)........................................ -0.778 Level 3 cache line reuse (data)........................................ 3.871 Level 2 cache hit rate (data).......................................... -3.496 Level 3 cache hit rate (data).......................................... 0.795 Level 1 cache read miss ratio (instruction)............................ 0.001 Level 1 cache miss ratio (data)........................................ 0.035 Level 2 cache miss ratio (data)........................................ 0.046 Level 3 cache miss ratio (data)........................................ 0.125 Bandwidth used to level 1 cache (MB/s)................................. 246.564 Bandwidth used to level 2 cache (MB/s)................................. 2052.984 Bandwidth used to level 3 cache (MB/s)................................. 438.146 MFLOPS (cycles)........................................................ 608.682 MFLOPS (wall clock).................................................... 604.235 MIPS (cycles).......................................................... 3042.594 MIPS (wall clock)...................................................... 3020.365 CPU time (seconds)..................................................... 1885.920 Wall clock time (seconds).............................................. 1899.800 % CPU utilization...................................................... 99.269