Mark Dechene

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Bio

I am a Ph.D. candidate in the Computer Engineering department at NC State. My research targets performance opportunities in manycore processor microarchitectures.

I received my B.S. in ECE from Marquette. Then, I worked as an EE at Motorola, where I did digital logic design for the OnStar vehicle module. While there, I took part-time graduate classes in ECE at Northwestern, but left for greener (warmer) pastures before it amounted to a degree.

I have twice interned at Intel's Oregon Computer Architecture group (ORCA) in Hillsboro, Oregon, where I functioned as a microprocessor architect on the upcoming Haswell core. Haswell is somewhere down the product pipeline following the Nehalem (Core i7) architecture. During my first stint, I was an out-of-order architect. During my second stint, I was an architect somewhere under the performance umbrella.