Professor and
Director of Graduate Programs

 Dr. Davis' research interests are in computer organization and architecture, with emphasis on highly parallel processing. Research on the architecture, development, and application of highly integrated, massively parallel machines is taking place within the "Blitzen project". A system based on an array of Blitzen processors is being evaluated for use in data acquisition and processing for the next generation particle collider at CERN, the European organization for nuclear research. Our investigations are directed toward performance and efficiency of architectural features, memory configurations, software development environments, and parallel algorithms.

 A separate activity is concerned with evaluation and use of new high performance parallel machines. We are investigating various systems for compute intensive problems such as air quality modeling. Issues include performance, exploiting parallelism, scalability of architecture with problem size, software portability, and parallel algorithm development.

Representative Publications

"A Software Approach to Avoiding Spatial Cache Collisions in Parallel Processor Systems", (with D. C. Wong and J. O. Young)  IEEE Trans. on Parallel and Distributed Systems,  Vol. 9, No. 6, June 1998, pp. 601-608.

 

"Real-Time Parallel Processing in High Energy Physics: Architecture of the Blitzen Data Acquisition System," (with S. Centro, et al), The Euromicro Journal, Vol. 40, pp 167-178.

 

"Evaluating Parallel Architectures for two Real-Time Applications with 100KHz Repetition Rate," (with J. Badier, et al), IEEE Trans. on Nuclear Science, Vol. 40, No. 1, February 1993, pp. 45-55.

 

"Issues and Applications Driving Research in Non-Conforming Massively Parallel Processors," (with T. Nordstrom, and B. Svensson), The New Frontiers: A Workshop on Future Directions of Frontiers of Massively Parallel Processing, I. Scherson, Editor, IEEE Computer Society Press, 1993.

 

"A Bit-Serial VLSI Array Processing Chip for Image Processing," (with R. A. Heaton and D. W. Blevins), IEEE Journal of Solid-State Circuits, Vol. 25, No. 2, April 1990, pp. 364-368.

 

(last update 23-Jul-98 by Auto-Format Script)