Hyperscalar Microarchitecture

This semester's Objective:

Devise methods to improve processor micro-scalability strictly by redesign of the hardware implementation. Prepare a report and simulation of an innovative scalable microprocessor for general purpose computing. The implementation will include a distributed register space and multiple instruction paths.

Some methods to be explored

Related Information

Access to some of this stuff is restricted, right now, because it is an active research topic. Please e-mail me if you would like more info. Much of this work is based on my efforts on ERL's CRAMPED project (now called SAND).

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David Winick.