Hyperscalar Microarchitecture

This semester's Objective:

Devise methods to improve processor micro-scalability strictly by redesign of the hardware implementation. Prepare a report and simulation of an innovative scalable microprocessor for general purpose computing. The implementation will include a distributed register space and multiple instruction paths.

Some methods to be explored

• Decouple F, D, C, and W stages, as well as E stage, of superscalar design.
• Decouple execution implementation from instruction set architecture.
• Build model of both control and data dependancies and anti-dependancies in register space.
• Multiple fetch PC's to reduce speculation.
• Prefetch stream buffers to relieve multiported cache design.
• Decode (pre) early, to detect control dependancies and manage task flow.
• Task management to avoid interrupts.
• ...

Related Information

• An overwelming argument for smarter or shorter speculative execution paths.
• A basic tree of calculations to validate the previous argument.
• The reason why superscalar control is so large and complicated (stall sources).
• The CRAMPED Architecture Register Renaming Policy, a superscalar research microprocessor being developed here in ERL.