This semester's Objective:
Devise methods to improve processor micro-scalability strictly by redesign
of the hardware implementation. Prepare a report and simulation of an
innovative scalable microprocessor for general purpose computing. The
implementation will include a distributed register space and multiple
Some methods to be explored
- Decouple F, D, C, and W stages, as well as E stage, of superscalar
- Decouple execution implementation from instruction set architecture.
- Build model of both control and data dependancies and
anti-dependancies in register space.
- Multiple fetch PC's to reduce speculation.
- Prefetch stream buffers to relieve multiported cache design.
- Decode (pre) early, to detect control dependancies and manage task
- Task management to avoid interrupts.
Access to some of this stuff is restricted, right now, because it is an
active research topic. Please e-mail me if you would like more info. Much of
this work is based on my efforts on ERL's CRAMPED project (now called SAND).
here to return to my Homepage.