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RESEARCH TRIANGLE PARK, N.C.--(BUSINESS WIRE)--Feb. 9, 2000-- The Semiconductor Research Corp. (SRC), in conjunction with contest co-sponsors Novellus Systems Inc., UMC and SpeedFam-IPEC, today announced five ``Phase One'' monetary winners, and ``Phase Two'' contestants in the SRC Copper IC Design Challenge.
Fifteen teams have now been selected from the field of 43 teams representing 34 universities from across North America to participate in ``Phase Two,'' the final phase of the contest. The ``Phase Two'' first, second and third place winners will be honored at SEMICON West 2000 in San Francisco.
The contest's objective is to create novel circuit designs that will help accelerate the adoption of new semiconductor copper technology by engaging the creative interest of university faculty and students. According to the contest sponsors, emerging semiconductor manufacturing technologies such as copper provide opportunities to create new design architectures that can significantly improve the functionality and performance of integrated circuits (ICs) and the systems in which they will be used. The sponsors hope to leverage the creativity available at leading engineering universities to speed the adoption of novel new approaches to IC design at the 0.18-micron node.
``I am pleased to announced the top five 'Phase One' winning proposals, although it wasn't easy to pick only five winners. The winning universities are Carnegie Mellon University, led by Professor Gary Fedder; Georgia Institute of Technology, led by Professor James Meindl; North Carolina State University, led by Professor Paul Franzon; University of Florida, led by Professor Kenneth O; and University of Minnesota, led by Professor Ramesh Harjani,'' said Larry Sumney, the SRC's president and CEO. ``Each team leader has been presented a check for $20,000 at the International Solid State Circuits Conference held in San Francisco. We now move on to 'Phase Two,' the final phase in our challenge. In this next round, all 15 participating university teams will have the opportunity to submit a winning IC design that uses the enhanced properties of copper interconnects to improve circuit performance and functionality. We hope that the design knowledge that we have gained with the implementation of this contest will prove valuable to the semiconductor industry as we move to copper as the new interconnect metal for sub-0.18-micron technologies.''
The SRC Copper Design Challenge offers over $150,000 in cash prizes and $850,000 in technical services and design implementation support. The submissions leveraged the power of copper interconnects and have focused on five areas: interconnect architecture, digital implementation, mixed-signal implementation, technology/component and wireless/RF (radio frequency).
In July 1999, 44 university teams submitted design proposals to compete in Phase One of the contest. The universities' paper designs were evaluated by a panel of judges made up of representatives from the SRC and the contest sponsors. Participants had access to UMC's 0.18-micron process copper libraries, provided by Artisan Components in partnership with UMC. The libraries were free-of-charge and available via downloads from Artisan's web site at www.artisan.com.
``Phase Two'' of the contest will be conducted during the Spring 2000 semester. During this phase the 15 participating teams will enter their layouts (in GDSII format) for actual silicon fabrication at UMC. The fabricated devices will then be returned to the contestants for test and evaluation. Contestants will then be expected to submit measured performance data and a discussion, comparing this data with simulation data, to the judges. The judges will select an overall winner to be announced at SEMICON West 2000. The final winners will be invited to present their designs at TECHCON 2000 in Phoenix. A $30,000 first-place award will be made to the winning team's university in the name of the team leader. A $20,000 second place award and a $10,000 third place award will also be granted. The cash prizes will support IC design education programs at the universities and allow a monetary reward for participating students on the winning teams.
The evaluation criteria for ``Phase Two'' will focus on creativity of design, impact of the design on future applications, design efficiency, test procedures, correlation of test results to the design performance predicted in Phase One and completeness of the materials submitted. All rights to designs submitted remain with the university or universities from which they originate.
About the Semiconductor Research Corporation
SRC, based in Research Triangle Park, N.C., with an office in San Jose, Calif., is the largest continuous industry-driven university research program in the United States. The SRC plans and manages a $35 million program of basic and applied research carried out principally at North American universities on behalf of participating North American companies. SRC can be found on the web at www.src.org.
About Novellus Systems
Novellus Systems Inc. manufactures, markets and services advanced automated wafer fabrication systems for the deposition of thin films. Novellus deposition systems are designed for high-volume production of advanced, leading-edge semiconductors at the lowest overall cost. Headquartered in San Jose, Calif., with subsidiaries in the United Kingdom, France, Germany, the Netherlands, China, Japan, Korea, Singapore and Taiwan, Novellus is a publicly traded company on the Nasdaq stock exchange (Nasdaq:NVLS - news). Additional information about the company is available on Novellus' home page on the World Wide Web, located at www.novellus.com.
UMC is a world leading semiconductor foundry group consisting of United Microelectronics Corp. (UMC), United Semiconductor Corp. (USC), United Integrated Circuits Corp. (UICC), United Silicon, Inc. (USIC), UTEK Semiconductor Corp. (UTEK) and the first dedicated foundry in Japan, Nippon Foundry Inc. (NFI). UMC leads the dedicated foundry industry in value-added design support with its Gold IPTM program. UMC companies are headquartered in Taiwan, with marketing and customer support offices located in the United States, Japan and the Netherlands. UMC's U.S. offices are located at 788 Palomar Avenue, Sunnyvale, Calif., 94086, tel. 408/733-8881, fax 408/733-8090. The company's website address is www.umcgroup.com.
SpeedFam-IPEC, Inc. designs, develops, manufactures, markets and
supports chemical mechanical planarization (CMP) systems used in the
fabrication of semiconductor devices and other high-throughput
precision surface processing systems. SpeedFAM-IPEC's flat surface
processing systems are used in the thin film memory disk media,
silicon wafer and general industrial components markets. The company
also markets and distributes polishing liquids (slurries), parts and
consumables used in its customers' manufacturing processes.
SpeedFam-IPEC, Inc. owns a 50-percent interest in each of two joint
ventures, SpeedFAM-IPEC Co., Ltd. (the Far East Joint Venture) and
LIST OF WINNING UNIVERSITIES AND PROJECTS Fifteen Phase II Contestants Five Phase I Winners University Project Carnegie Mellon Micromachined Tunable On-chip University High-Q Resonator Georgia Institute of High Performance Clock and Power Technology Distribution Networks for Gigascale Integration Using Copper Interconnects North Carolina State A High-Speed & High-Capacity Single-Chip University Copper Crossbar University of Florida A Wireless Clock Distribution System: Clock Receiver and Transmitter Circuits University of Minnesota RF Front-End Design with Copper Passive Components University Project Illinois Institute of ESD Protection Design Using Copper Technology Interconnects; More Robustness and Less Parasitics Kansas State University Design of Integrated RF Bandpass Filters and Oscillators using Copper Interconnects Michigan State Micro-learner: a Self Programming Engine University for Real-time Estimation, Prediction and Control North Carolina State Monolithic Copper Integrated Circuitry University Supporting Multi-layer MEMS Ohio State University High Performance GHz RF CMOS IC's for Integrated Phase-Locked Loops Rensselaer Polytechnic Institute Crosstalk Checker University of Fast and Reconfigurable Image California, San Diego Compression System-on-Chip for Mobile Communication Using Cu Technology University of Illinois The Design of New Current-Mode Sense at Champaign Urbana Amplifiers for High Speed DRAM with Copper Interconnects University of Virginia Routing VIAs and Other Optimizations for Copper Interconnects Yale University The UltraC2K: A Wire-Intensive Superscalar Processor
Semiconductor Research Corporation Richard LaScala, 919/941-9444, (Fax) 919/941-9450 email@example.com or MCA Jennifer Hrycyszyn, 650/968-8900, (Fax) 650/968-8990 firstname.lastname@example.org
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